1. Technical Field
The present invention relates to semiconductor memory devices and methods of fabricating the same, and more particularly, to semiconductor memory devices having a plurality of vertical cell transistors sharing one planar cell transistor, and methods of fabricating the same.
2. Discussion of the Related Art
While a DRAM device has an advantage of accomplishing high integration more easily in comparison with other memory devices such as an SRAM device, it has difficulty maintaining stored charges, which are reduced with demand of a size reduction of the device, due to soft errors generated by leakage currents of memory cells, inner noise, and alpha particles from the exterior. Therefore, the memory cells of such devices require a refresh operation periodically in order to maintain the data stored in the memory cells. Further, power consumption is increased even in a standby state.
Also, flash memory devices or EEPROM devices have an advantage of not requiring an operation of refreshing memory cells in order to maintain the data stored in the memory cells. However, the flash memory device has a drawback in improving a relatively low access speed since it takes a relatively long time to program its memory cells. Further, a high voltage is required to program (write) or erase the memory cells of the flash memory device. A high electric field applied during erase and program operations degrades quality of a tunnel barrier layer which is formed of an oxide layer. The phenomenon becomes more serious when the number of times of performing erase and program operations increases. If the number of times of the erase and program operations is increased up to about 105, the function of the tunnel barrier layer, which is formed of an oxide layer, is degraded. As a result, the memory device has a limited life time.
Therefore, it is required to provide a new memory cell having the advantages of the DRAM and flash memory devices. That is, it is required to provide a semiconductor memory device having scalable memory cells with long-term data maintenance (nonvolatile), a low operation voltage, a high speed, a high reliability, and a high integration. A new memory cell referred to as a scalable two transistor memory cell (STTM cell) has been proposed by Nakazato, et. al. (U.S. Pat. No. 5,952,692). According to Nakazato, et. al., the new memory cell is referred to as a planar localized electron device memory (PLEDM) cell. As the memory cell has an electrically isolated memory node (floated memory node), it is excellent in resistance to soft errors and has a high signal-to-noise ratio (S/N ratio), thereby providing a high gain. Further, the memory cell operates at room temperature without degradation by hot carriers, and can be fabricated using an existing silicon formation process. FIG. 1A is a sectional view of a conventional scalable two-transistor memory (STTM) cell, FIG. 1B is a schematic circuit diagram illustrating a conventional STTM cell, and FIG. 1C is a sectional view illustrating a conventional program transistor.
As shown in FIGS. 1A to 1C, the STTM cell includes a sensing (lower) transistor 1 known as a read or access transistor, and a program (upper) transistor 2 known as a write transistor. The program transistor 2 is a MOS transistor having a multiple tunnel junction barrier layer 4 (hereinafter, referred to as MTJ barrier layer) between source and drain regions, and a vertical two sidewalls gate. The sensing transistor 1 includes a drain region 7 and a source region 8 formed in a semiconductor substrate 18. The sensing transistor 1 is a typical MOS transistor including a floating gate 6 functioning as a storage node of a memory cell, a drain region 7 functioning as a sensing line corresponding to a bit line, and a source region 8 receiving an applied ground voltage or a specific voltage.
As shown in the same drawings, a channel region is formed between the drain region 7 and the source region 8 of the sensing transistor 1, and a first gate insulating layer 3 is formed on the channel region.
Further, as shown in the same drawings, the program transistor 2 is stacked on a gate of the sensing transistor in the STTM cell. The storage node functioning as the floating gate 6 of the sensing transistor also functions as a drain of the program transistor. A control gate line 11 formed on the sidewalls of the MTJ barrier layer 4 and the floating gate 6 functions as a write line or a word line. The source region of the program transistor functions as a data line 12. A second gate insulating layer 5 is interposed between the control gate line 11 and the data line 12. The MTJ barrier layer is formed by alternately stacking an insulating layer 13 and a semiconductor layer 14.
A data voltage is applied to the data line 12 in a write mode, and a write voltage, that is, a program voltage, is applied to the control gate (or write) line 11. Thus, since a barrier height between the data line 12 and the floating gate 6 is reduced, a tunneling current flows through insulating layers constituting the MTJ barrier layer. As a result, charges (electrons or holes) are stored in the floating gate 6. The stored charges change a threshold voltage of the sensing transistor 1. For example, in the case that electrons are stored in the floating gate 6, and the sensing transistor 1 is an NMOS transistor, a threshold voltage of the sensing transistor is increased toward a positive voltage. The write operation of the STTM cell can be conducted using a write voltage lower than that of a flash memory device. This is because the charge injection into the floating gate 6 is controlled by the control gate line 11 together with the data line 12.
In order to read the data stored in the STTM cell, a read voltage is applied to the control gate line 11, and an appropriate voltage is applied to the source region 8. Then, the current flowing through the drain region 7 is detected by a sensing amplifier (not shown). In this case, if the threshold voltage of the sensing transistor 1 is higher than the read voltage, a current does not flow through the source region 7. However, if the threshold voltage of the sensing transistor 1 is lower than the read voltage, a current flows through the source region 7.
In the STTM cell as described above, the floating gate 6 is completely surrounded by an insulating material layer unlike the storage node of the DRAM cell. That is, the floating gate 6 is floated. Thus, in the case that the read voltage is much lower than the write voltage, the memory cell need not be refreshed. On the other hand, the control gate line may be classified as a first control gate line controlling the sensing transistor, and a second control gate line controlling the program transistor. In this case, even though the write voltage is almost equal to the read voltage, the program transistor is not turned on during the read operation. Thus, it is not required to refresh the memory cell regardless of the difference between the write voltage and the read voltage.
The STTM cell must be reduced in size with the increase of an integration degree of a semiconductor IC before being formed on a semiconductor substrate. In the STTM cell formed on the semiconductor substrate, a minimum feature size (or minimum design rule) means a minimum size being formable by a photolithography technology. Since a photolithography process must be performed in order to form the STTM cell, there is a limitation to reducing the minimum feature size.
Further, since the channel length of the sensing transistor in the STTM cell is short, it is difficult to achieve a thin junction depth of the source/drain regions. Specifically, in the case that the channel is ultra short, there occur phenomena such as a short channel effect and a drain induced barrier lowering, thereby degrading operation characteristics of the STTM cell.
Furthermore, in the STTM cell, the area ratio between a memory cell and interconnection lines is large.